An important feature of an amplifier arrangement for use as a (transmission) line driver is high output voltage swing while maintaining desirably high linearity. Thus, such an amplifier arrangement requires significant quiescent current output--i.e., significant output current in the absence of input signal--in order to suppress sudden jumps ("kicks") in the output current when the output turns on, such jumps otherwise causing undesirable distortion. Accordingly, Class A or Class AB amplifier operation is indicated for advantageous operation of line to be driven, for such operation supplies the desired quiescent current.
In a paper entitled "A Programmable CMOS Dual Channel Interface Processor for Telecommunications Applications," published in IEEE Journal of Solid-State Circuits, SC-19, (6), pp. 892-899 (Dec. 1984), B. K. Ahuja et al. teach a complementary Class AB output buffer arrangement (at p. 895, FIG. 3) in which a double-ended preamplifier drives a negative input terminal of each of a pair of error amplifiers. One of these error amplifiers controls an output p-channel MOS transistor ("PMOS transistor"), and the other controls an output n-channel MOS transistor ("NMOS transistor"). These transistors are connected in series between positive and negative power supply voltages, thereby forming a load device. For the purpose of furnishing negative feedback to the error amplifiers, a node between the output transistors is connected to the positive input terminal of each of the error amplifiers, and this node serves as an output point of the output buffer arrangement.
There is, however, a major shortcoming in the above-described arrangement: the open-loop voltage gain of the error amplifiers of the Class AB arrangement is limited to less than about 8 or 10, in order that the quiescent output current should not undesirably fluctuate in response to random effects (such as random offset voltages). Such a relatively low open-loop gain, however, does not supply the high linearity that is desired for many practical applications unless the output transistors are operated in their saturation regions. However, in such a case (of saturation operation), in order to retain the desirably high linearity, undesirably large output transistor sizes are required--whereby there results undesirably high quiescent power dissipation, unwanted loss of bandwidth due to the large capacitance associated with the output transistors, and a requirement of undesirably large silicon area for these transistors. Moreover, in the absence of applied input signals--i.e., in the quiescent state of the amplifier--a Class AB (or a Class A) amplifier dissipates undesirably large amounts of power.
Another arrangement was taught in a paper by J. A. Fischer, entitled "A High-Performance CMOS Power Amplifier," published in IEEE Journal of Solid-State Circuits, SC-20, pp. 1200-1205 (December 1985). In that paper, a conventional common-drain stage was added to the above-described circuit taught by B. K. Ahuja et al., in order to achieve a well-controlled quiescent state. In circuit applications in which linearity is important, a significant main disadvantage of the arrangement taught by J. A. Fischer et al. is an undesirable non-linearity produced by a turning off by the transistors in the common-drain stage midway through voltage swings. This turning off results in an undesirably poor overall linearity, especially for high output voltage swings. It would therefore be desirable to have an amplifier circuit arrangement that mitigates these shortcomings.